1. Field of the Invention
The present invention relates to the layout of a memory cell array in a semiconductor memory, and more particularly to a technology for reducing the chip size of a semiconductor memory.
2. Description of the Related Art
Semiconductor memories have sense amplifiers for amplifying data that is read out from memory cells to bit lines. In addition, nonvolatile semiconductor memories such as a flash memory have voltage generators for supplying a high voltage or a low voltage to source lines according to memory operations. U.S. patent application Ser. No. 5,293,350 has disclosed a technique in which a sense amplifier, a voltage generator, and the like are shared among a plurality of bit lines and the like, to reduce the chip size of the semiconductor memory.
FIGS. 1A and 1B show the essential parts of a semiconductor memory of this type. FIG. 1A shows the circuit configuration and FIG. 1B shows a sectional structure of the area that is shown by the broken lines in FIG. 1A.
A memory cell array 1 is provided with bit lines BL0 and BL1, which are connected to its memory cells (not shown). The bit lines BL0 and BL1 are connected to a sense amplifier 3 (or a voltage generator etc.) through transistors 2a and 2b respectively and a common signal line CMN. The gates of the transistors 2a and 2b are connected to control lines 4a and 4b respectively. The control lines 4a and 4b are laid perpendicular to the bit lines BL0 and BL1.
In this semiconductor memory, when the memory cell array is in a read operation, one of the control lines 4a and 4b is changed to a high level, turning ON either of the transistors 2a and 2b. It follows that one of the bit lines BL0 and BL1 is connected to the sense amplifier 3 through the common signal line CMN, whereby the data read out from a memory cell to the bit line BL0 (or BL1) is amplified. That is, the sense amplifier 3 is shared between the bit lines BL0 and BL1.
As shown in FIG. 1B, the transistor 2a is composed of diffusion layers (a source S and a drain D) which are formed in a semiconductor substrate SUB, and a control line 4a which is laid on the semiconductor substrate SUB via a gate insulator. The source S of the transistor 2a is connected to the common signal line CMN. The drain D of the transistor is connected to the bit line BL0. Since the broken-lined area of FIG. 1A allows no transistor that has the control line 4b as its gate, the source and the drain (diffusion layers) corresponding to the control line 4b are not formed in the semiconductor substrate SUB.
FIG. 2 shows an overview of the fabrication process for forming the source S and the drain D of the transistor 2a. 
The source S and the drain D are formed by implanting ions into the semiconductor substrate SUB with the gate of the transistor 2a (the control line 4a) as a mask. To form the transistor 2a, a photoresist 5 is initially applied to over the semiconductor substrate SUB (wafer) and then baked. Next, exposure is performed using a photomask 6, followed by development, so that the photoresist 5 is processed into a shape corresponding to the photomask 6 as shown in FIG. 2. Subsequently, as shown by the arrows in the diagram, phosphorus or other ions are implanted selectively to form the source S and the drain D of the transistor 2a. Here, no ion is implanted into the regions covered under the photoresist 5 (outside of the source S and the drain D of the transistor 2a). Thus, no transistor having the control line 4b as its gate is formed in the broken-lined area of FIG. 1A.
As shown in FIG. 1A, the control lines 4a and 4b to be the gates of the transistors 2a and 2b are laid perpendicular to the bit lines BL0 and BL1. The transistors 2a and 2b are formed by implanting ions with these control lines 4a and 4b as masks. This requires that regions undesired of transistor formation (for example, the regions adjacent to the control line 4b within the broken-lined area of FIG. 1A) must be masked with the photoresist 6. In other words, to selectively connect the bit lines BL0 and BL1 to the sense amplifier 3 and the like, the photoresist 6 needs to be opened for each of the transistors 2a and 2b corresponding to the bit lines BL0 and BL1, respectively.
The openings in the photoresist 6 must be made with predetermined margins from the regions to form transistors and those not to form transistors. Owing to these margins, there has been a problem of an increased layout area when the wiring spacing between the control lines 4a and 4b needs to be extended beyond the formable minimum process size. Since the increased layout area grows the chip size of the semiconductor memory, there has been a problem of a rise in product costs. The memory cell array and its peripheral regions (sense-amplifier regions etc.) contain a number of identical circuits arranged repeatedly. On this account, an increase in the layout area of these regions has a significant impact on the product costs of the semiconductor memory.
It is an object of the present invention to improve the integration level of a memory cell array and its periphery to reduce the chip size of a semiconductor memory.
According to one of the aspects of the present invention, a semiconductor memory has a plurality of memory cell rows, an input/output circuit for inputting/outputting data to/from the memory cell rows, and a plurality of first transistor rows arranged for each of the memory cell rows. The memory cell rows include a plurality of memory cells connected in series. For example, the memory cells are nonvolatile memory cells each having a control gate and a floating gate, and the memory cell rows are configured as a NAND type.
The first transistor rows have a plurality of transistors connected in series. For example, the memory cell rows are connected to the first transistor rows through local bit lines, respectively. The first transistor rows are connected to the input/output circuit through a global bit line, which is common to these transistor rows.
In each first transistor rows, a switching transistor operates as a switch while a short transistor(s) each having a source and a drain shorted to each other function(s) as wiring. When performing a read/write operation from/to the memory cells, any of the switches (transistors) among the plurality of first transistor rows turns on to selectively connect any of the memory cell rows to the input/output circuit. That is, the input/output circuit is shared among the plurality of memory cell rows.
The first transistor rows are provided with the plurality of transistors in advance regardless of whether or not to use the transistors as switches. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the pattern shape of the photomask corresponding to the ion-implanted regions (the layout rule of the diffusion layer regions) need not be taken account of when arranging the spacing between the transistors of the first transistor rows (the wiring spacing of the gate material). Since the transistors can be arranged closely, the layout area of the first transistor rows can be reduced. This allows a reduction in the chip size of the semiconductor memory. The present invention offers a high effect when applied to nonvolatile semiconductor memories of NAND type which feature high integration.
According to another aspect of the present invention, the semiconductor memory is provided with a plurality of the memory cell rows corresponding to each of the first transistor rows. These memory cell rows are respectively connected to a corresponding transistor row of the first transistor rows through selecting transistors in each of the memory cell rows. Since any of the memory cell rows are selectively connected to the corresponding transistor row of the first transistor rows by the selecting transistors, the first transistor rows can be shared among a plurality of memory cell rows. As a result, the input/output circuit can be shared among a greater number of memory cell rows and the chip size can be reduced.
According to another aspect of the present invention, in each of the first transistor rows, the source and the drain of the short transistor not to be operated as a switch are shorted to each other by using metal wiring. The metal wiring is formed in a latter stage of the semiconductor fabrication processes after the formation of the transistors of the transistor rows. Therefore, for example, when prototyping the semiconductor memory, even if a mistake is found in a position of the transistor to be operated as a switch in each of the first transistor rows, this mistake can be corrected by simply changing the photomask in the wiring process. Conventionally, when such mistake is found, a makeover from the process of forming the diffusion layers (the source and the drain of the transistor) was needed.
According to another aspect of the present invention, the semiconductor memory has a voltage generator for supplying a predetermined voltage to the unselected memory cell row(s) among the memory cell rows, and a plurality of second transistor rows arranged for each of the memory cell rows. The second transistor rows include a plurality of transistors connected in series. For example, the memory cell rows are connected to the first and second transistor rows through local bit lines, and the second transistor rows are connected to the voltage generator through a bit control line, which is common to these transistor rows.
In each of the second transistor rows, a switching transistor operates as a switch while a short transistor(s) each having a source and a drain shorted to each other function(s) as wiring. When performing a read/write operation from/to the memory cells, any of the switches (transistors) among the plurality of second transistor rows turn(s) on to selectively connect any of the memory cell rows to the voltage generator. That is, the voltage generator is shared among the plurality of memory cell rows. The voltage generator supplies, for example, a first voltage and a second voltage to the local bit line(s) of the unselected memory cell row(s), respectively, when the selected memory cell row among the memory cell rows performs a read operation and a write operation.
The second transistor rows are provided with the plurality of transistors in advance. Since there is no need to selectively form only such a transistor that is to be operated as a switch, there is no need to form ion-implanted regions for making a source and a drain per transistor. As a result, the pattern shape of the photomask corresponding to the ion-implanted regions (the layout rule of the diffusion layer regions) need not be taken account of when arranging the spacing between the transistors of the second transistor rows (the wiring spacing of the gate material). Since the transistors can be arranged closely, the layout area of the second transistor rows can be reduced. This allows a reduction in the chip size of the semiconductor memory.
According to another aspect of the present invention, the input/output circuit and the voltage generator are arranged on both sides of the memory cell rows. On this account, the input/output circuit and the voltage generator can be efficiently arranged in the peripheral regions of the memory cell rows without increasing the layout area.
According to another aspect of the present invention, in each of the second transistor rows, the source and the drain of the short transistor not to be operated as a switch are shorted to each other by using metal wiring. The metal wiring is formed in a latter stage of the semiconductor fabrication processes after the formation of the transistors of the transistor rows. Therefore, for example, when prototyping the semiconductor memory, even if a mistake is found in position of the transistor to be operated as a switch in each of the second transistor rows, this mistake can be corrected by simply changing the photomask in the wiring process.